A failed EMC scan is rarely a surprise to anyone who looked at the layout. Emissions and susceptibility are set by where the current actually flows, and that is fixed the moment the copper is committed. What happens at the test house is measurement, not causation.
The decisions that matter are mostly about return paths. A signal returns directly beneath its trace on the nearest plane, so a split or a gap in that plane forces the return current around the discontinuity and turns the resulting loop into an antenna. Reference changes at layer transitions do the same thing unless a stitching via gives the return somewhere to go. Decoupling that is electrically distant from the pin it serves does not decouple much, whatever the schematic says.
The other half is what leaves the board. Cables are efficient radiators, so anything driven off-board — and anything with a connector on it — deserves attention at the point it crosses the boundary: filtering placed at the connector rather than near the driver, and a clean chassis reference for shield connections.
None of this is exotic, and none of it costs money at design stage. It costs a great deal after a failed scan, because the fixes available then are ferrites, shielding cans and enclosure changes — expensive per unit, forever. A layout review before release is a couple of hours against the alternative of a respin and a second test booking.